Mainframe Performance Topics Podcast Episode 0 “Sic Parvis Magna” (“Greatness From Small Beginnings”)

(Originally posted 2016-03-17.)

I’m delighted Marna Walle and I are collaborating on a podcast series. We’re calling it “Mainframe, Performance, Topics Podcast”. You can guess where we got the name from. 🙂

Below are the show notes.

The series is here.

Episode 0 is here.

Episode 0 “Sic Parvis Magna” ( “Greatness From Small Beginnings" ) Show Notes

Here are the show notes for Episode 0 “Sic Parvis Magna” ( “Greatness From Small Beginnings" ).

We’re structuring each podcast episode (loosely) in three parts:

We’ll post useful links and supplementary information in each episode’s show notes.


Our “Mainframe” topic is about an SPE to z/OS 2.1 for SDSF.


APARs mentioned were:


Our “Performance” topic is about detecting address spaces in support of FPGA cards.

FPGA Card Support Address Space Detection

Some useful information on the new PCIE and FPGHWAM address spaces is here.


Other things we discussed were:

And if you think Naughty Dog made up “sic parvis magna” see here.

Contacting Us

You can reach Marna on Twitter as mwalle and by email.

You can reach Martin on Twitter as martinpacker and by email.

Or you can leave a comment below.

Published by Martin Packer

I'm a mainframe performance guy and have been for the past 35 years. But I play with lots of other technologies as well.

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