Wouldn’t you like to know where in the machine an LPAR’s memory is? Perhaps not but for some customers it’s more than a matter of idle curiosity. The good news is that RMF will be able to tell you: A recent APAR for z/OS 3.2 Data Gatherer OA68545 exploits information from z17 processors to provideContinue reading “Memories Are Made Of This”
Tag Archives: drawer
Prepare To Evacuate
It is rare to need to evacuate hardware. But being rare is not an excuse to neglect to plan for it. Obviously I’ve been sensitised to the question by real customer situations – though I don’t intend to describe the situations in any detail; This post should prove useful enough without doing that. When IContinue reading “Prepare To Evacuate”
Engineering – Part 8 – Remote Access Detection
The fact we’re up to “Part 8” illustrates there’s a lot to talk about once you take performance analysis down to the individual logical / physical processor level. Many people have talked about the need to avoid LPARs crossing processor drawer boundaries. There are good reasons for this – because access to cache or memoryContinue reading “Engineering – Part 8 – Remote Access Detection”
Drawers And More
Late last year I wrote a blog post: Drawers, Of Course. I’ll admit I’d half forgotten about it. Now that a few months have passed it’s time to write about at least part of it again. So why write about it again now? I’ve so much more experience with the instrumentation I described in thatContinue reading “Drawers And More”
Drawers, Of Course
This post is about processor drawers and how the topic might influence your LPAR design. Introduction Once upon a time drawers and books were very simple. If you wanted a certain number of processors – whether GCP, zIIP, zAAP, IFL, or ICF – that determined the number of drawers you had. (I’m still hearing peopleContinue reading “Drawers, Of Course”
Mainframe, Performance, Topics 