In Drawers And More I mentioned Parking with the words One day I’ll be able to colour VL’s according to whether they are parked or not – or rather fractions of the interval they’re parked. That’s a not very difficult fix for the python code. Well, that proved as simple as I thought. So, alongContinue reading “Relating Parked Time To Cores”
Tag Archives: performance
Drawers And More
Late last year I wrote a blog post: Drawers, Of Course. I’ll admit I’d half forgotten about it. Now that a few months have passed it’s time to write about at least part of it again. So why write about it again now? I’ve so much more experience with the instrumentation I described in thatContinue reading “Drawers And More”
Drawers, Of Course
This post is about processor drawers and how the topic might influence your LPAR design. Introduction Once upon a time drawers and books were very simple. If you wanted a certain number of processors – whether GCP, zIIP, zAAP, IFL, or ICF – that determined the number of drawers you had. (I’m still hearing peopleContinue reading “Drawers, Of Course”
Mainframe Performance Topics Podcast Episode 34 “Homeward Bound”
We started planning this one quite a while ago. Thankfully our topics tend to be evergreen – in that they’re still topical for quite a while. In that vein I know we are gaining new listeners and they aren’t all starting with the latest episode. Anyway, our schedules have been their usual hectic selves –Continue reading “Mainframe Performance Topics Podcast Episode 34 “Homeward Bound””
Bursty Batch – Small Reprise
In Bursty Batch I talked about how some customers have large amounts of batch work coming in all at once, and how a new WLM function in z/OS 3.1 might be handy in catering for it. And it subsequently occurred to me there is a cheap-to-collect and therefore almost universal method of assessing how burstyContinue reading “Bursty Batch – Small Reprise”
In My Estimation
This post is about Coupling Facility sizing – particularly when you don’t have one to start with. And particularly CPU. (Memory is reasonably catered for with CFSizer – whether over the web or now in z/OSMF for z/OS 3.1.) And the reason I’m writing about this is because I was recently asked to help sizeContinue reading “In My Estimation”
Bursty Batch
Bursty batch is quite common. For example, a customer I’m dealing with right now kicks off a burst of batch at 7PM and another burst at 10PM. I doubt that customer is reading this blog post. Another customer has a burst of batch kicking off at 2AM. They probably will read this post. But theirContinue reading “Bursty Batch”
z16 ICA-SR Structure Service Times
It was recently brought to my attention that CFLEVEL 25, made available with IBM z16, improved ICA-SR links. (I don’t know why I didn’t spot this before – but it’s documented in several places, including IBM Db2 13 for z/OS Performance Topics, an interesting Redbook. (I actually read this from cover to cover during aContinue reading “z16 ICA-SR Structure Service Times”
Mainframe Performance Topics Podcast Episode 33 “These Boots Were Made”
I hope you can tell that Marna and I had a lot of fun making this episode. I can’t recall which of us came up with the cultural reference. But it sort of developed – until the aftershow was sort of inevitable. Anyhow here are the show notes for Episode 33. The podcast series isContinue reading “Mainframe Performance Topics Podcast Episode 33 “These Boots Were Made””
Reporting For Duty?
I’m writing this on a flight to Munich, where I’m presenting Parallel Sysplex Resiliency at a customer conference. By the way I wonder what happened to the word “resilience” and what the difference is between that and “resiliency”. But, it’s a trip to a nice city and I expect to run into lots of friendsContinue reading “Reporting For Duty?”