Tag Archives: performance

Mainframe Performance Topics Podcast Episode 35 “In Search Of EXCELence?”

As usual it’s taken us longer than we would like. The usual problem of finding planning and recording slots we can both make applies. But I think the episode turned out well. It was certainly fun to make. So here are the show notes. Episode 35 “In Search Of EXCELence?” long show notes This episodeContinue reading “Mainframe Performance Topics Podcast Episode 35 “In Search Of EXCELence?””

Utility Window Detection

It seems to me understanding when an installation’s utilities run is important. Why is this? It’s because utilities can make systems behave differently from how they usually do. And some of these behaviours can represent a challenge. It’s often also valuable to reduce the utility window. What Is A Utility? There is no formal definitionContinue reading “Utility Window Detection”

Engineering – Part 9 – Perhaps Affinity Nodes Are Interesting After All

I’ve tended to think Affinity Nodes aren’t worthy of study – because there’s little you can do to influence them. However, that doesn’t mean one shouldn’t understand them. (In this post I’m going to say “processor” when I mean “logical processor” and “affnode” when I mean “affinity node”. Also “VL” for “Vertical High”, “VM” forContinue reading “Engineering – Part 9 – Perhaps Affinity Nodes Are Interesting After All”

Engineering – Part 8 – Remote Access Detection

The fact we’re up to “Part 8” illustrates there’s a lot to talk about once you take performance analysis down to the individual logical / physical processor level. Many people have talked about the need to avoid LPARs crossing processor drawer boundaries. There are good reasons for this – because access to cache or memoryContinue reading “Engineering – Part 8 – Remote Access Detection”

Engineering – Part 7 – RMF Processor Home Address Fields

I was recently asked where I was getting the home addresses for logical processors from in RMF SMF 70. I will agree the fields I use are not that easy to interpret – so here’s my go at making them more accessible. Along the way I’ll also talk about SMF 74 Subtype 4 Coupling FacilityContinue reading “Engineering – Part 7 – RMF Processor Home Address Fields”

Relating Parked Time To Cores

In Drawers And More I mentioned Parking with the words One day I’ll be able to colour VL’s according to whether they are parked or not – or rather fractions of the interval they’re parked. That’s a not very difficult fix for the python code. Well, that proved as simple as I thought. So, alongContinue reading “Relating Parked Time To Cores”

Drawers, Of Course

This post is about processor drawers and how the topic might influence your LPAR design. Introduction Once upon a time drawers and books were very simple. If you wanted a certain number of processors – whether GCP, zIIP, zAAP, IFL, or ICF – that determined the number of drawers you had. (I’m still hearing peopleContinue reading “Drawers, Of Course”

Mainframe Performance Topics Podcast Episode 34 “Homeward Bound”

We started planning this one quite a while ago. Thankfully our topics tend to be evergreen – in that they’re still topical for quite a while. In that vein I know we are gaining new listeners and they aren’t all starting with the latest episode. Anyway, our schedules have been their usual hectic selves –Continue reading “Mainframe Performance Topics Podcast Episode 34 “Homeward Bound””

Bursty Batch – Small Reprise

In Bursty Batch I talked about how some customers have large amounts of batch work coming in all at once, and how a new WLM function in z/OS 3.1 might be handy in catering for it. And it subsequently occurred to me there is a cheap-to-collect and therefore almost universal method of assessing how burstyContinue reading “Bursty Batch – Small Reprise”